There is a trend in the communications industries to develop digital systems that provide more efficient transmission of information. This development is found in digital cellular telephone systems, facsimile transmission systems, data networking systems, and video distribution systems. A number of systems have recently been proposed for distributing information in digital data form using Asynchronous Transfer Mode (ATM) technology.
ATM technology has been designed with the intention of providing service for a wide variety of applications such as voice, video, and data. Each of these applications has different service requirements in terms of cell loss, time delay, and cell delay variation. For example, voice traffic can withstand a small amount of cell loss, but it is rather intolerant to time delay and cell delay variation. Due to the asynchronous statistical nature of ATM, voice traffic must be smoothed at the receiver end in order to eliminate any accumulated cell delay variation incurred in the network. The requirements for video traffic are somewhat dependent upon coding and compression schemes. These coding schemes can produce either constant bit-rate or variable bit-rate traffic. Data services can withstand a considerable amount of time delay and cell delay variation, but cannot lose any information, or else retransmission is required. Video traffic can typically tolerate a small amount of cell loss, however, it is sensitive to time delay and cell delay variation, and asynchronous transport of video creates a number of problems as discussed more fully below.
Various wideband digital distribution networks have been proposed for offering subscribers an array of video services, including true Video On Demand Service. For example, U.S. Pat. No. 5,247,347 to Litteral et al., assigned in common with the present invention and incorporated herein in its entirety by reference, integrates a public switched telephone network with video-on-demand service. A Digital Cross-connect System (DCS) receives compressed video data from a video provider and supplies the video data to selected central office (CO) interfaces. Electronic devices associated with the subscriber loops modify the transmission characteristics of the subscriber loops to permit delivery of full motion video information over existing loop plant facilities.
Such wideband distribution networks transport digitized, compressed video program information supplied from a video headend in order to improve transport efficiency. For example, MPEG (moving picture experts group) is a broad generic standard for digital video program compression. A number of specific compression algorithms satisfy MPEG requirements. MPEG-2 is a second generation compression standard capable of encoding video program material into a 6 Mbits/sec bit stream and packetizing a number of 6 Mbits/sec channel streams into a single higher rate signal transport stream.
At the subscriber premises, the digital compressed program stream transported by the wideband digital distribution networks must be recovered in order to provide the video information to video display systems for displaying the video information to the subscribers. Unlike a computer data file composed of data downloaded from a remote server for use in a local computer, certain applications such as voice reproduction and presentation of animated video requires synchronous presentation in order to provide intelligible information to the user. Video data, by definition, consists of "real-time" information, requiring synchronization of the encoding and decoding processes to insure accurate real-time reproduction for viewing. Various MPEG receiver systems have been developed to synchronize MPEG decoders to a received MPEG-encoded stream. Basic MPEG receiver systems synchronize internal clocks to received time stamp values, known as Program Clock Reference (PCR) values, by sampling the PCR values, calculating the difference between the sampled PCR values and counted internal clock values (C) between PCR samples to obtain an error signal, and outputting an error signal to the internal clock to synchronize the internal clock according to the calculated difference.
U.S. Pat. No, 5,396,497 to Veltman discloses an MPEG I demultiplexer/decoder including a clock producing a time reference, and a demultiplexing switch separating a composite data stream into audio sample batches, audio time stamps, video frames, and video time stamps. The disclosed demultiplexer/decoder also includes an audio phase locked loop that produces an audio timing signal in response to the audio time stamps and time reference, and a video phase-locked loop that produces a video timing signal in response to the video time stamps and the timing signal. The audio timing signal and the video timing signal are supplied to audio and video decoders, respectively. Data packets in the MPEG I stream, referred to as a system clock reference (SCR), are used to control the transfer data rate in the decoder. The SCR is used during initialization of the device in order to synchronize the phase-locked loops with the respective data streams.
U.S. Pat. No. 5,381,181 to Deiss discloses a clock recovery apparatus for an MPEG I decoded signal. According to Deiss, the receiver comprises a counter, responsive to a controlled receiver clock signal, that is sampled at the arrival of a count value embedded in the MPEG transport layer. The differences of successive sampled count values from the receiver counter are compared with the differences of corresponding successive values of the MPEG count value in the MPEG transport layer to provide a signal to control the receiver clock signal.
FIG. 1 is a simplified block diagram of the clock recovery apparatus disclosed in Deiss. The clock recovery apparatus comprises a PCR detector 10 that receives a MPEG I-encoded data stream. The MPEG stream comprises count values, denoted program clock references (PCR), embedded as auxiliary data within the transport packets. As disclosed in Deiss, these PCRs are supplied during encoding of the video signal as presentation time stamps in order to provide lip synchronization of associated audio and video information at the receiver.
The PCR detector 10 produces a control pulse 10a to a counter 12 upon the detection of a PCR value in the data stream. The counter 12 is driven by a voltage controlled oscillator (VCXO) 14. Upon receiving the control pulse 10a, the counter 12 outputs the count value to a subtraction circuit 16, and resets itself to restart counting modulo 230 in response to the count pulses from the VCXO 14. The subtractor 16 calculates an error signal (E) in response to the differences between the detected PCR values from the MPEG stream and the counted values (L) latched from the counter 12. Thus, according to Deiss, the error signal E is calculated by the subtractor 16 according to the following equation: EQU E=.vertline.PCR.sub.n -PCR.sub.n-1 .vertline.-.vertline.L.sub.n L.sub.n-1.vertline.
The calculated error signal E is passed through a low pass filter 18 and then applied to the VCXO 14, designed to operate substantially at 27 MHz. The error signal E is utilized to condition the voltage controlled oscillator 14 to a frequency tending to equalize the differences between the counted values output by the counter 12 and the detected PCR values from the MPEG stream to enable the MPEG stream to be decoded by the MPEG decoder 20. Thus, Deiss contemplates adjusting the system clock to synchronize with the detected PCR stream.
As disclosed in Deiss, the digital video signal transmission arrangement generates presentation time stamps (PTRs) in response to a fixed frequency 27 MHz clock in the encoder. In addition, the receiver system of Deiss is intended to perform the inverse function of the encoder and transmitting modem at the transmitting headend. As such, Deiss assumes that there is no differential delay in the transport of the MPEG encoded stream, such that the detected PCR values at the receiver end represent an interarrival time corresponding to the interdeparture time defined by the system clock at the encoder.
However, attempts to improve the core switching, multiplexing and transmission technologies in integrated digital networks for transport of voice, data and video services to multiple users may cause differential delays in the transport of the digital data. ATM provides broad-bandwidth, low delay, packet switching and multiplexing at speeds of 1.544 Mbit/s to 1.2 gigabits per second (Gbit/s), whereby usable capacity can be assigned dynamically (on demand) by allocating bandwidth capacity to fixed-sized information-bearing units called "cells". Each cell contains header and information fields. The ATM standard, CCITT.121/2 specifies a 53 byte cell which includes a 5 byte header and a 48 byte payload.
The conversion of MPEG-2 data into ATM cell format, however, may impose differential timing delays due to the transport of the ATM cells throughout the network. The "asynchronous" nature of ATM causes timing problems in reception and reproduction of certain types of broadband information.
Further, certain transmission protocols may require a stream of continuous data. Thus, an ATM data stream carrying MPEG video data may need to be padded with ATM idle cells, or "dummy cells", in order to ensure proper synchronization with the physical layer. Adding such idle cells may create delays between the ATM cells carrying the respective PCR values of the MPEG stream. Moreover, delays in the ATM cell stream are introduced each time an ATM cell stream passes through an ATM switch. Finally, different ATM cell streams may be multiplexed together to improve transport efficiency in the broadband network. For example, commonly-assigned, copending application Ser. No. 08/380,744, filed Jan. 31, 1995, entitled "Full Service Network Using Asynchronous Transfer Mode Multiplexing" (attorney ref: 680-109), the disclosure which is incorporated in its entirety by reference, discloses an ATM edge device which is used to multiplex a plurality of ATM cells from different input sources onto a reduced number of output paths by combining the cell streams from the different sources.
The delay imposed by each of these different ATM processes varies over time, for example as a function of the data rates of input cells and resultant loading on each ATM processing device. For such reasons, the delay imposed on one cell in a particular stream may vary with respect to the next cell in the same stream.
Thus, an ATM cell stream passing through different ATM network components undergoes cell delay variation, whereby the cell transport rate at a receiving end is different than the cell transport rate at the transmitting end. In other words, ATM transport of MPEG-encoded information causes a variation in the interarrival time between the MPEG packets carried by the ATM cells. The cell delay variation may create a delay on the order of one millisecond, causing the synchronous payload data within the received ATM cell stream to lose the data rate originally output at the transmitting end before conversion to an ATM cell stream. Thus, the reconstructed MPEG stream may have PCR values that do not accurately reflect the interarrival time for the MPEG stream segment due to the differential delay caused by the cell delay variation. Thus, transport through an ATM network creates jitter in the MPEG stream caused by cell delay variation ATM cells carrying the MPEG stream.
As discussed above, the prior art receiver systems assume no differential delay in the PCR values stored in the MPEG stream and assure a uniform, constant delay between data packets. Thus, these prior art systems would be unable to compensate for jitter in the received MPEG stream. Moreover, the jitter in the received MPEG stream in FIG. 1 may cause a miscalculation in the error signal (E) supplied to the VCXO 14, resulting in a loss of synchronization. Thus, any jitter in a received MPEG stream would result in a degradation in receiver performance.
Moreover, a data stream passing through an ATM network receives additional cell delay variation each time the data stream passes through another network component (also referred to as network element or network node), such as an ATM switch. As networks become more complex, data streams may have a greater tendency to reach an unacceptable level of cell delay variation unless the cell delay variation at each node is carefully monitored. Further, the amount of cell delay variation may increase as the performance of a network node deteriorates over time due to hardware or software failures, or traffic overload.